verilator

mirror of https://github.com/verilator/verilator.git synced 2026-10-06 01:54:01 +02:00

Files

T

Geza Lore 02e64f0795 Optimize multiplexers in Dfg synthesis (#6331 )

The previous algorithm was designed to handle the general case where a
full control flow path predicate is required to select which value to
use when synthesizing control flow join point in an always block.

Here we add a better algorithm that tries to use the predicate of
the closest dominating branch if the branch paths dominate the joining
paths. This is almost universally true in synthesizable logic (RTLMeter
has no exceptions), however there are cases where this is not
applicable, for which we fall back on the previous generic algorithm.

Overall this significantly simplifies the synthesized Dfg graphs and
enables further optimization.

2025-08-25 13:47:45 +01:00