28 lines
866 B
Systemverilog
28 lines
866 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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logic a, b, c, d, e;
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default clocking @(posedge clk);
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endclocking
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// Two ranged cycle delays in one intersect operand is unsupported
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assert property ((a ##[1:3] b ##[1:2] c) intersect (d ##2 e));
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// Single common length, but an operand is not a plain boolean sequence
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assert property ((a throughout (b ##1 c)) intersect (d ##[0:2] e));
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// Both operands vary over a range and carry internal structure
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assert property ((a ##[1:3] (b ##1 c)) intersect (d ##[2:4] e));
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// Operand top-level delay fixed but length varies via a nested range
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assert property ((a ##2 (b ##[1:3] c)) intersect (d ##[3:5] e));
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endmodule
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