58 lines
1.6 KiB
Systemverilog
58 lines
1.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define checkd(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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// verilog_format: on
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module t (
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input clk
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);
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integer cyc = 0;
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reg [63:0] crc = 64'h5aef0c8d_d70a4497;
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wire a = crc[0];
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wire b = crc[1];
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wire c = crc[2];
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wire d = crc[3];
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int f_fix = 0;
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int f_dis = 0;
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always_ff @(posedge clk) begin
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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if (cyc == 99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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default clocking @(posedge clk);
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endclocking
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// An intersect whose operands share no common length compiles and never
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// matches (IEEE 1800-2023 16.9.6 requires a window of equal length). Each
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// form is the antecedent of `|-> 1'b0`: it stays vacuous while it never
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// matches, so the else fires once per match -- pinned to 0. A spurious match
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// would both fail the assertion and bump the counter.
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// Unequal fixed lengths: {2} vs {3}.
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ap_fix :
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assert property (disable iff (cyc < 2) ((a ##2 b) intersect (c ##3 d)) |-> 1'b0)
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else f_fix <= f_fix + 1;
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// Disjoint ranges: {1,2} vs {4,5}.
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ap_dis :
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assert property (disable iff (cyc < 2) ((a ##[1:2] b) intersect (c ##[4:5] d)) |-> 1'b0)
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else f_dis <= f_dis + 1;
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final begin
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`checkd(f_fix, 0); // Questa: 0
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`checkd(f_dis, 0); // Questa: 0
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end
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endmodule
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