131 lines
4.4 KiB
Systemverilog
131 lines
4.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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`define checkd(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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// IEEE 1800-2023 16.9.10: seq1 within seq2
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// CRC-driven random stimulus. Each property has a counter; at cyc==99 we
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// `checkd` against Verilator's actual count and record the Questa golden
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// value in a trailing comment for cross-simulator reference.
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module t (
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input clk
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);
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integer cyc = 0;
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reg [63:0] crc = '0;
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// Non-adjacent CRC bits (gap > max delay) to avoid LFSR correlation.
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wire a = crc[0];
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wire b = crc[7];
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wire c = crc[15];
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wire d = crc[23];
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int count_p1 = 0;
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int count_p2 = 0;
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int count_p3 = 0;
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int count_p4 = 0;
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int count_p5 = 0;
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int count_p6 = 0;
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int count_p7 = 0;
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int count_p8 = 0;
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int count_p9 = 0;
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int count_p10 = 0;
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// Boolean within boolean: equivalent to `a && b`.
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assert property (@(posedge clk) disable iff (cyc < 10)
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(a & b) |-> (a within b))
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count_p1 <= count_p1 + 1;
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// Boolean within constant true: always passes when a is high.
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assert property (@(posedge clk) disable iff (cyc < 10)
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a |-> (a within 1'b1))
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count_p2 <= count_p2 + 1;
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// `a` must hold at some offset within the c ##1 d window.
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cover property (@(posedge clk) disable iff (cyc < 10)
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a within (c ##1 d))
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count_p3 <= count_p3 + 1;
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// `a` within a length-3 outer (four possible offsets).
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cover property (@(posedge clk) disable iff (cyc < 10)
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a within (c ##3 d))
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count_p4 <= count_p4 + 1;
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// Equal-length inner/outer: single offset, reduces to intersect.
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assert property (@(posedge clk) disable iff (cyc < 10)
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(a & c) |-> ((a ##1 1'b1) within (c ##1 1'b1)))
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count_p5 <= count_p5 + 1;
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// Inner length 1, outer length 3 -> three offsets (0, 1, 2).
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cover property (@(posedge clk) disable iff (cyc < 10)
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(a ##1 b) within (c ##3 d))
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count_p6 <= count_p6 + 1;
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// Inner length 2, outer length 3 -> two offsets (0, 1).
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cover property (@(posedge clk) disable iff (cyc < 10)
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(a ##2 b) within (c ##3 d))
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count_p7 <= count_p7 + 1;
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// within nested inside intersect: both must match equal length.
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cover property (@(posedge clk) disable iff (cyc < 10)
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((a ##1 b) within (c ##2 d)) intersect (a ##2 b))
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count_p8 <= count_p8 + 1;
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// within combined with throughout on the outer: throughout's rhs
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// fixedLength still feeds into within.
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cover property (@(posedge clk) disable iff (cyc < 10)
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a within (a throughout (b ##1 c)))
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count_p9 <= count_p9 + 1;
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// within on the RHS of intersect: forces the parser into the direct
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// `sexpr yWITHIN sexpr` grammar rule (IEEE 1800-2023 17.7.1) rather
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// than the pexpr-copied variant used at property top level.
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cover property (@(posedge clk) disable iff (cyc < 10)
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(a ##3 b) intersect ((c ##1 d) within (a ##3 b)))
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count_p10 <= count_p10 + 1;
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always_ff @(posedge clk) begin
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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if (cyc == 0) begin
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crc <= 64'h5aef0c8d_d70a4497;
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end
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else if (cyc == 99) begin
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`checkh(crc, 64'hc77bb9b3784ea091);
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// p1/p2/p5 use |->; the NFA currently fires the pass action on
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// vacuous passes too, so counts are inflated vs. Questa. Pre-existing
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// engine-wide behavior, not within-specific.
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`checkd(count_p1, 89); // Questa: 23
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`checkd(count_p2, 89); // Questa: 44
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`checkd(count_p3, 26); // Questa: 20
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`checkd(count_p4, 24); // Questa: 22
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`checkd(count_p5, 89); // Questa: 26
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`checkd(count_p6, 21); // Questa: 16
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`checkd(count_p7, 15); // Questa: 9
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`checkd(count_p8, 15); // Questa: 4
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`checkd(count_p9, 17); // Questa: 10
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`checkd(count_p10, 24); // Questa: 15
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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// Harness for stand-alone simulators (e.g. QuestaSim). Verilator uses
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// test_regress's built-in clock shell and ignores this module.
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`ifndef VERILATOR
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module wrap;
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logic clk = 0;
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always #5 clk = ~clk;
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t inst (.clk(clk));
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endmodule
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`endif
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