177 lines
6.9 KiB
Systemverilog
177 lines
6.9 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t (
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input clk
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);
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integer cyc = 0;
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reg [63:0] crc = '0;
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reg [63:0] sum = '0;
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// Derive test signals from CRC
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wire a = crc[0];
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wire b = crc[1];
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wire c = crc[2];
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wire d = crc[3];
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// Aggregate outputs into a single result vector
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wire [63:0] result = {60'h0, d, c, b, a};
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always_ff @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x a=%b b=%b c=%b d=%b\n",
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$time, cyc, crc, a, b, c, d);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
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if (cyc == 0) begin
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= '0;
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end else if (cyc < 10) begin
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sum <= '0;
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end else if (cyc == 99) begin
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`checkh(crc, 64'hc77bb9b3784ea091);
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`checkh(sum, 64'hdb7bc8bfe61f987e);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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// =========================================================================
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// Boolean and/or (single-cycle, CRC-driven antecedent)
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// =========================================================================
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// Boolean 'and': (a and b) true iff a && b
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assert property (@(posedge clk) disable iff (cyc < 2)
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(a and b) |-> (a & b));
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// Boolean 'or': (a or b) true iff a || b
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assert property (@(posedge clk) disable iff (cyc < 2)
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(a or b) |-> (a | b));
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// 'and' with constant true -- reduces to just 'a'
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assert property (@(posedge clk) disable iff (cyc < 2)
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(a and 1'b1) |-> a);
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// 'or' with constant false -- reduces to just 'a'
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assert property (@(posedge clk) disable iff (cyc < 2)
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(a or 1'b0) |-> a);
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// Logical '||' (AstLogOr) in a MULTI-CYCLE sequence: must trigger NFA
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// (single-cycle booleans skip NFA via hasMultiCycleExpr filter).
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cover property (@(posedge clk) (a || b) ##1 (a | b));
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// =========================================================================
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// Multi-cycle sequence and (IEEE 1800-2023 16.9.5)
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// CRC-driven: antecedent gates when sequence starts, consequent guaranteed
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// =========================================================================
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// Sequence 'and': both branches must complete, same length
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assert property (@(posedge clk)
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(a & b) |-> (a ##1 1'b1) and (b ##1 1'b1));
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// Sequence 'and': different lengths, end at later branch
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assert property (@(posedge clk)
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(a & b) |-> (a ##1 1'b1) and (b ##2 1'b1));
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// Sequence 'and': standalone (constant, always passes)
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assert property (@(posedge clk)
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(1'b1 ##1 1'b1) and (1'b1 ##2 1'b1));
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// =========================================================================
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// Multi-cycle sequence or (IEEE 1800-2023 16.9.7)
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// CRC-driven: at least one branch must complete
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// =========================================================================
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// Sequence 'or': same length, CRC-driven
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assert property (@(posedge clk)
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(a | b) |-> (a ##1 1'b1) or (b ##1 1'b1));
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// Sequence 'or': different lengths, CRC-driven
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assert property (@(posedge clk)
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(a | b) |-> (a ##1 1'b1) or (b ##2 1'b1));
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// Sequence 'or': standalone (constant, always passes)
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assert property (@(posedge clk)
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(1'b1 ##1 1'b1) or (1'b1 ##2 1'b1));
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// Sequence 'or' where both branches end in registered state (no finalCondp).
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// Exercises guardedLink(termVertexp,...) in buildOrCombiner for both sides.
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cover property (@(posedge clk) (a[*2]) or (b[*2]));
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// Sequence 'and' with unbounded range on one side -- marks combiner unbounded.
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cover property (@(posedge clk) (a ##[1:$] b) and (c ##1 d));
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// =========================================================================
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// SAnd edge cases (NFA builder coverage)
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// =========================================================================
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// SAnd where only one side has finalCondp: a[*2] has no finalCond (consumed
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// by ConsRep); b ##1 c has finalCond=c. Exercises single-cond path in
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// buildAndCombiner.
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cover property (@(posedge clk) (a[*2]) and (b ##1 c));
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// SAnd where both sides lack finalCondp (both end with registered state).
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// Exercises buildMatchNow(!condp) path.
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cover property (@(posedge clk) (a[*2]) and (b[*2]));
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// =========================================================================
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// Negated cover property (NFA assembleResult negated+cover branches)
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// Different shapes to cover the matchCondp/rejectBasep/throughoutRejectp
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// combinations in the negated+cover code path.
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// =========================================================================
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// Shape A: finalCondp=b, required-step reject (the canonical case).
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cover property (@(posedge clk) not (a ##1 b));
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// Shape B: seq ends in state machine -> finalCondp is null.
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cover property (@(posedge clk) not (a ##1 (b[*2])));
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// Shape C: throughout in the seq -> throughoutRejectp non-null.
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cover property (@(posedge clk) not (a throughout (b ##1 c)));
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// Shape D: throughout with state-ending RHS (no finalCondp) -> matchCondp null,
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// throughoutRejectp non-null. Exercises the `if (throughoutRejectp) notPMatchp =
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// orExprs(...)` branch in assembleResult.
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cover property (@(posedge clk) not (a throughout (b[*2])));
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// Assert variants for the negated-assert code path (needAccept branches).
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assert property (@(posedge clk) not (a ##1 (b[*2])))
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else $display("negated multi-cycle fail");
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assert property (@(posedge clk) not (a throughout (b ##1 c)))
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else $display("negated throughout fail");
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// Negated assert with an explicit pass-action block -- exercises the
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// `VL_DO_DANGLING(pushDeletep(passsp), passsp)` branch in the needAccept path.
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assert property (@(posedge clk) not (a ##1 b))
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$display("negated with pass action");
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// Negated assert ending in state machine (matchCondp null, rejectBasep only):
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// exercises the `else if (rejectBasep)` branch of notPMatchp assembly.
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assert property (@(posedge clk) not (a ##1 (b[*2])))
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$display("negated state-end with pass");
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// Negated assert throughout with state-ending RHS (matchCondp null,
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// throughoutRejectp non-null): exercises the `if (throughoutRejectp)` branch.
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assert property (@(posedge clk) not (a throughout (b[*2])))
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else $display("negated throughout state-end");
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// Negated assert with throughout AND an explicit pass-action: needAccept is
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// true (pass block set), so assembleResult runs with outMatchpp!=null and
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// throughoutRejectp non-null, exercising the needAccept-path throughout
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// branch of notPMatchp assembly.
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assert property (@(posedge clk) not (a throughout (b ##1 c)))
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$display("negated throughout with pass action");
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endmodule
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