58 lines
1.3 KiB
Systemverilog
58 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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class Cls;
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int x;
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int int_q[$];
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int dyn[];
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function new();
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x = 0;
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int_q = '{12, 13, 17, 19};
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dyn = '{21, 22, 23};
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endfunction
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task rand_with_queue();
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int ok;
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ok = std::randomize(x) with {x inside {int_q};};
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`checkd(ok, 1);
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`checkd(int_q.size(), 4);
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`checkd(int_q[0], 12);
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`checkd(int_q[1], 13);
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`checkd(int_q[2], 17);
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`checkd(int_q[3], 19);
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if (!(x inside {int_q})) `stop;
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endtask
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task rand_with_dyn();
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int ok;
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ok = std::randomize(x) with {x inside {dyn};};
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`checkd(ok, 1);
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`checkd(dyn.size(), 3);
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`checkd(dyn[0], 21);
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`checkd(dyn[1], 22);
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`checkd(dyn[2], 23);
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if (!(x inside {dyn})) `stop;
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endtask
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endclass
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module t;
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Cls obj;
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initial begin
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obj = new();
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repeat (20) obj.rand_with_queue();
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repeat (20) obj.rand_with_dyn();
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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