21 lines
423 B
Systemverilog
21 lines
423 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Zhi QU
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input logic [3:0] v,
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output logic [6:0] y
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);
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assign y[0] = !|v;
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assign y[1] = !&v;
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assign y[2] = !^v;
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assign y[3] = !~^v;
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assign y[4] = !^~v;
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assign y[5] = !~&v;
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assign y[6] = !~|v;
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endmodule
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