27 lines
568 B
Systemverilog
27 lines
568 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Zhi QU
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// SPDX-License-Identifier: CC0-1.0
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interface decoupled_ifc;
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logic ready;
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endinterface
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module t (
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output wire out
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);
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logic a = 1'b0; // declaration initialization
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assign a = 1'b1; // continuous assignment
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assign out = a;
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// OK as two different instances
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decoupled_ifc ifc_in ();
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decoupled_ifc ifc_out ();
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initial ifc_out.ready = 0;
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assign ifc_in.ready = ifc_out.ready;
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endmodule
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