50 lines
1.3 KiB
Systemverilog
50 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// The code describes a very simple hierarchy of modules.
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// The lowest level instantiates avst_interface with name my_avst_if.
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// The highest level also instantiates the same interface type
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// with the exact same name. The file should lint with no errors
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// or warnings other than those disabled by lint_off.
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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/* verilator lint_off DECLFILENAME */
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/* verilator lint_off UNUSEDSIGNAL */
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interface avst_interface;
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logic ready;
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logic valid;
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modport sink_mp(output ready, input valid);
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endinterface
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module child (
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output logic ready_out
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);
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avst_interface my_avst_if ();
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assign ready_out = my_avst_if.ready;
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assign my_avst_if.ready = 1'b1; // drives child.my_avst_if.ready only
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endmodule
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module wrapper (
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avst_interface.sink_mp my_avst_if
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);
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child child_inst (
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.ready_out(my_avst_if.ready) // sole driver of outer my_avst_if.ready
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);
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endmodule
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module top (
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input logic in_valid,
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output logic out_ready
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);
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avst_interface my_avst_if ();
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assign my_avst_if.valid = in_valid;
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assign out_ready = my_avst_if.ready;
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wrapper wrapper_inst (.my_avst_if(my_avst_if));
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endmodule
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