32 lines
963 B
Systemverilog
32 lines
963 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2026 by Antmicro.
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
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// verilog_format: on
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typedef struct packed {logic [31:0] value;} Entry;
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typedef struct packed {Entry [1:0][1:0] entries;} DataBlock;
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module sub;
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DataBlock data_block;
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endmodule
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module t;
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sub sub1 ();
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logic [31:0] forced_value;
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initial begin
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forced_value = 32'h00000001;
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force sub1.data_block.entries[0][0].value = forced_value[31:0];
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`checkh(sub1.data_block.entries[0][0].value[0], 1'b1);
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`checkh(sub1.data_block.entries[0][0].value, 32'h00000001);
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$finish;
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end
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endmodule
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