29 lines
908 B
Systemverilog
29 lines
908 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Test for --binary --vpi runtime library loading. The design provides its
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// own clock (so the simulation has Verilog event activity); the VPI library
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// (t_flag_main_vpi.cpp), loaded at runtime via +verilator+vpi+, observes
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// 'count' via a cbValueChange callback and calls $finish after MAX_TICKS
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// edges. Signals are public so the library can reach them by name
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// (requires --public-flat-rw).
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module t;
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reg clk /*verilator public_flat_rw*/;
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reg [31:0] count /*verilator public_flat_rw*/;
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initial begin
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clk = 0;
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count = 0;
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end
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// Self-driving clock: the design itself keeps the simulation alive
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always #5 clk = ~clk;
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always @(posedge clk) count <= count + 1;
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endmodule
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