27 lines
517 B
Systemverilog
27 lines
517 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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module t;
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bit clk = 0;
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int cyc = 0;
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initial forever #1 clk = ~clk;
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always @(posedge clk) begin
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cyc = cyc + 1;
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if (cyc >= 10) $finish;
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end
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always @(posedge clk) begin
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fork
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begin
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while ($sampled(cyc) != 99) #1;
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if (cyc >= 10) $stop;
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end
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join_none
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end
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endmodule
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