73 lines
2.1 KiB
Systemverilog
73 lines
2.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module - Edge case: negative value ranges
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// This file ONLY is placed into the Public Domain, for any use, without warranty.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Test: Bins with negative value ranges
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// Expected: Should handle negative numbers correctly
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// verilog_format: off
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`define stop $stop
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`define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t (
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input clk
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);
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int signed value;
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covergroup cg;
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cp_neg: coverpoint value {
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bins negative = {[-100 : -1]};
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bins zero = {0};
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bins positive = {[1 : 100]};
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bins mixed = {[-10 : 10]};
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}
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endgroup
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cg cg_inst = new;
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int cyc = 0;
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always @(posedge clk) begin
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cyc <= cyc + 1;
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case (cyc)
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0: value <= -50; // Hit negative bin
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1: value <= 0; // Hit zero bin
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2: value <= 50; // Hit positive bin
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3: value <= -5; // Hit mixed bin (also negative)
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4: value <= 5; // Hit mixed bin (also positive)
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5: begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endcase
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cg_inst.sample();
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// Coverage progression (NBA assignments committed before sample() within always block)
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// cyc=0: value=-50 -> hits 'negative' only -> 1/4=25%
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// cyc=1: value=0 -> hits 'zero' + 'mixed' (both match) -> 3/4=75%
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// cyc=2: value=50 -> hits 'positive' -> 4/4=100%
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// cyc=3: value=-5 -> 'negative' + 'mixed' already hit -> 4/4=100%
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// cyc=4: value=5 -> 'positive' + 'mixed' already hit -> 4/4=100%
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if (cyc == 0) begin
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`checkr(cg_inst.get_inst_coverage(), 25.0);
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end
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if (cyc == 1) begin
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`checkr(cg_inst.get_inst_coverage(), 75.0);
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end
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if (cyc == 2) begin
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`checkr(cg_inst.get_inst_coverage(), 100.0);
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end
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if (cyc == 3) begin
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`checkr(cg_inst.get_inst_coverage(), 100.0);
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end
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if (cyc == 4) begin
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`checkr(cg_inst.get_inst_coverage(), 100.0);
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end
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end
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endmodule
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