46 lines
1.5 KiB
Systemverilog
46 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2026 by Wilson Snyder.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Test the graceful-degradation safety net for embedded covergroups (the dominant
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// UVM pattern: a covergroup declared inside a class whose coverpoints reference the
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// enclosing object's members). Such a covergroup is lowered into a sibling class
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// with no handle to the enclosing instance, so emitting it would produce
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// uncompilable C++ ("invalid use of non-static data member"). Until the enclosing
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// back-pointer feature exists, Verilator must emit a clean COVERIGN warning and skip
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// lowering the covergroup, rather than crashing the C++ compile.
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class ubus_transfer;
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bit [15:0] addr;
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bit read_write;
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endclass
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class ubus_master_monitor;
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ubus_transfer trans_collected;
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// Coverpoints reference 'trans_collected', a member of the enclosing class.
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// A cross is included so the safety-net cleanup also exercises cross removal.
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covergroup cov_trans;
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trans_start_addr: coverpoint trans_collected.addr {option.auto_bin_max = 16;}
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trans_dir: coverpoint trans_collected.read_write;
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trans_addr_x_dir : cross trans_start_addr, trans_dir;
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endgroup
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function new();
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trans_collected = new;
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cov_trans = new;
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endfunction
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endclass
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module t;
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ubus_master_monitor m;
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initial begin
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m = new;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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