328 lines
11 KiB
Systemverilog
328 lines
11 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Test cross coverage: 2-way, 3-way, and 4-way crosses
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// verilog_format: off
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`define stop $stop
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`define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t;
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logic [1:0] addr;
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logic cmd;
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logic mode;
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logic parity;
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typedef struct packed {logic m_p; logic h_mode;} cfg_t;
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cfg_t s_cfg = '0;
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// 2-way cross
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covergroup cg2;
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cp_addr: coverpoint addr {bins addr0 = {0}; bins addr1 = {1};}
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cp_cmd: coverpoint cmd {bins read = {0}; bins write = {1};}
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addr_cmd: cross cp_addr, cp_cmd;
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endgroup
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// 3-way cross
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covergroup cg3;
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cp_addr: coverpoint addr {bins addr0 = {0}; bins addr1 = {1}; bins addr2 = {2};}
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cp_cmd: coverpoint cmd {bins read = {0}; bins write = {1};}
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cp_mode: coverpoint mode {bins normal = {0}; bins debug = {1};}
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addr_cmd_mode: cross cp_addr, cp_cmd, cp_mode;
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endgroup
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// 4-way cross
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covergroup cg4;
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cp_addr: coverpoint addr {bins addr0 = {0}; bins addr1 = {1};}
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cp_cmd: coverpoint cmd {bins read = {0}; bins write = {1};}
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cp_mode: coverpoint mode {bins normal = {0}; bins debug = {1};}
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cp_parity: coverpoint parity {bins even = {0}; bins odd = {1};}
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addr_cmd_mode_parity: cross cp_addr, cp_cmd, cp_mode, cp_parity;
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endgroup
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// Cross with option set inside the cross body
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covergroup cg5;
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cp_addr: coverpoint addr {bins addr0 = {0}; bins addr1 = {1};}
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cp_cmd: coverpoint cmd {bins read = {0}; bins write = {1};}
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addr_cmd_opt: cross cp_addr, cp_cmd{option.weight = 2;}
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endgroup
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// 2-way cross where one coverpoint uses a range bin
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covergroup cg_range;
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cp_addr: coverpoint addr {
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bins lo_range = {[0 : 1]}; // range bin
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bins hi_range = {[2 : 3]};
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}
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cp_cmd: coverpoint cmd {bins read = {0}; bins write = {1};}
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addr_cmd_range: cross cp_addr, cp_cmd;
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endgroup
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// Cross where one coverpoint has ignore_bins - ignored values must not appear in cross bins
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covergroup cg_ignore;
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cp_addr: coverpoint addr {
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ignore_bins ign = {3}; // addr=3 excluded from cross
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bins a0 = {0};
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bins a1 = {1};
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}
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cp_cmd: coverpoint cmd {bins read = {0}; bins write = {1};}
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cross_ab: cross cp_addr, cp_cmd;
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endgroup
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// Cross with option.at_least set in the cross body
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covergroup cg_at_least;
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cp_addr: coverpoint addr {bins addr0 = {0}; bins addr1 = {1};}
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cp_cmd: coverpoint cmd {bins read = {0}; bins write = {1};}
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addr_cmd_al: cross cp_addr, cp_cmd{option.at_least = 3;}
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endgroup
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// Cross with option.goal set in the cross body
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covergroup cg_goal;
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cp_addr: coverpoint addr {bins addr0 = {0}; bins addr1 = {1};}
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cp_cmd: coverpoint cmd {bins read = {0}; bins write = {1};}
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addr_cmd_goal: cross cp_addr, cp_cmd{option.goal = 90;}
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endgroup
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// Cross with an unsupported option (option.per_instance) - Verilator warns and ignores it
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covergroup cg_unsup_cross_opt;
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cp_addr: coverpoint addr {bins addr0 = {0}; bins addr1 = {1};}
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cp_cmd: coverpoint cmd {bins read = {0}; bins write = {1};}
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addr_cmd_unsup: cross cp_addr, cp_cmd{
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option.per_instance = 1; // unsupported for cross - expect COVERIGN warning
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}
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// Non-standard hierarchical reference as a cross item (an implicit coverpoint):
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// accepted with NONSTD, but implicit coverpoints are unsupported so the whole
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// cross is dropped (COVERIGN, suppressed here) - it contributes no bins.
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/* verilator lint_off NONSTD */
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cross_hier: cross cp_addr, s_cfg.m_p;
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/* verilator lint_on NONSTD */
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endgroup
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// Covergroup with an unnamed cross - the cross is reported under the default name "cross"
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covergroup cg_unnamed_cross;
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cp_a: coverpoint addr {bins a0 = {0}; bins a1 = {1};}
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cp_c: coverpoint cmd {bins read = {0}; bins write = {1};}
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cross cp_a, cp_c; // no label: reported under the default cross name
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endgroup
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// Cross plus an un-crossed coverpoint: get_inst_coverage must combine the converted
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// (VlCoverpoint) coverpoint cp_solo with the legacy cross/crossed-coverpoint bins.
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covergroup cg_mixed;
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cp_addr: coverpoint addr {bins addr0 = {0}; bins addr1 = {1};}
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cp_cmd: coverpoint cmd {bins read = {0}; bins write = {1};}
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cp_solo: coverpoint mode {bins normal = {0}; bins debug = {1};} // not crossed
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ab: cross cp_addr, cp_cmd;
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endgroup
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// Crossed (hence non-convertible) coverpoint that also has a default bin: exercises the
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// legacy default-bin codegen path that converted coverpoints bypass.
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covergroup cg_def_cross;
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cp_a: coverpoint addr iff (mode) {bins a0 = {0}; bins a1 = {1}; bins ad = default;}
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cp_c: coverpoint cmd {bins read = {0}; bins write = {1};}
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axc: cross cp_a, cp_c;
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endgroup
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cg2 cg2_inst = new;
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cg_ignore cg_ignore_inst = new;
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cg_range cg_range_inst = new;
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cg3 cg3_inst = new;
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cg4 cg4_inst = new;
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cg5 cg5_inst = new;
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cg_at_least cg_at_least_inst = new;
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cg_goal cg_goal_inst = new;
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cg_unsup_cross_opt cg_unsup_cross_opt_inst = new;
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cg_unnamed_cross cg_unnamed_cross_inst = new;
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cg_mixed cg_mixed_inst = new;
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cg_def_cross cg_def_cross_inst = new;
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initial begin
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// Sample 2-way: hit all 4 combinations
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// cg2: 2 cp bins + 2 cp bins + 4 cross bins = 8 bins total (flat count)
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addr = 0;
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cmd = 0;
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mode = 0;
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parity = 0;
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cg2_inst.sample(); // addr0 x read
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`checkr(cg2_inst.get_inst_coverage(), 37.5); // 3/8: addr0, read, addr0_x_read
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addr = 1;
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cmd = 1;
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mode = 0;
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parity = 0;
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cg2_inst.sample(); // addr1 x write
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`checkr(cg2_inst.get_inst_coverage(), 75.0); // 6/8: all cp bins + 2 cross bins
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addr = 0;
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cmd = 1;
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mode = 0;
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parity = 0;
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cg2_inst.sample(); // addr0 x write
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`checkr(cg2_inst.get_inst_coverage(), 87.5); // 7/8: 3 cross bins hit
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addr = 1;
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cmd = 0;
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mode = 0;
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parity = 0;
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cg2_inst.sample(); // addr1 x read
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`checkr(cg2_inst.get_inst_coverage(), 100.0); // 8/8: all 4 cross bins hit
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// Sample 3-way: hit 4 of 12 combinations
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// cg3: 3+2+2+12=19 bins; 4 cross bins hit -> 11/19=57.9% (not clean; no intermediate checkr)
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addr = 0;
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cmd = 0;
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mode = 0;
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cg3_inst.sample(); // addr0 x read x normal
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addr = 1;
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cmd = 1;
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mode = 0;
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cg3_inst.sample(); // addr1 x write x normal
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addr = 2;
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cmd = 0;
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mode = 1;
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cg3_inst.sample(); // addr2 x read x debug
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addr = 0;
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cmd = 1;
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mode = 1;
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cg3_inst.sample(); // addr0 x write x debug
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// Sample 4-way: hit 4 of 16 combinations
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// cg4: 2+2+2+2+16=24 bins; 4 cross bins hit -> 12/24=50%
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addr = 0;
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cmd = 0;
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mode = 0;
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parity = 0;
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cg4_inst.sample();
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addr = 1;
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cmd = 1;
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mode = 0;
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parity = 1;
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cg4_inst.sample();
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`checkr(cg4_inst.get_inst_coverage(), 37.5); // 9/24: all cp bins + 2 cross bins
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addr = 0;
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cmd = 1;
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mode = 1;
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parity = 0;
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cg4_inst.sample();
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addr = 1;
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cmd = 0;
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mode = 1;
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parity = 1;
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cg4_inst.sample();
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`checkr(cg4_inst.get_inst_coverage(), 50.0); // 12/24: all cp bins + 4 cross bins
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// Sample cg5 (cross with option.weight=2; weight is ignored in flat bin count)
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// cg5: 2+2+4=8 bins; 2 cross bins hit -> 6/8=75%
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addr = 0;
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cmd = 0;
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cg5_inst.sample();
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`checkr(cg5_inst.get_inst_coverage(), 37.5); // 3/8: addr0, read, addr0_x_read
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addr = 1;
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cmd = 1;
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cg5_inst.sample();
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`checkr(cg5_inst.get_inst_coverage(), 75.0); // 6/8: all cp bins + 2 cross bins
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// Sample cg_ignore: addr=3 is in ignore_bins so no cross bins for it
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// cg_ignore: 2+2+4=8 bins total
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addr = 0;
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cmd = 0;
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cg_ignore_inst.sample(); // a0 x read
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`checkr(cg_ignore_inst.get_inst_coverage(), 37.5); // 3/8
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addr = 1;
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cmd = 1;
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cg_ignore_inst.sample(); // a1 x write
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`checkr(cg_ignore_inst.get_inst_coverage(), 75.0); // 6/8
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addr = 0;
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cmd = 1;
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cg_ignore_inst.sample(); // a0 x write
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`checkr(cg_ignore_inst.get_inst_coverage(), 87.5); // 7/8
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addr = 1;
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cmd = 0;
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cg_ignore_inst.sample(); // a1 x read
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`checkr(cg_ignore_inst.get_inst_coverage(), 100.0); // 8/8
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addr = 3;
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cmd = 0;
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cg_ignore_inst.sample(); // ignored (addr=3 in ignore_bins)
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`checkr(cg_ignore_inst.get_inst_coverage(), 100.0); // still 100%
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// Sample range-bin cross
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// cg_range: 2+2+4=8 bins
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addr = 0;
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cmd = 0;
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cg_range_inst.sample(); // lo_range x read
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`checkr(cg_range_inst.get_inst_coverage(), 37.5); // 3/8
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addr = 2;
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cmd = 1;
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cg_range_inst.sample(); // hi_range x write
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`checkr(cg_range_inst.get_inst_coverage(), 75.0); // 6/8
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addr = 1;
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cmd = 1;
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cg_range_inst.sample(); // lo_range x write
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`checkr(cg_range_inst.get_inst_coverage(), 87.5); // 7/8
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addr = 3;
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cmd = 0;
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cg_range_inst.sample(); // hi_range x read
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`checkr(cg_range_inst.get_inst_coverage(), 100.0); // 8/8
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// Sample cg_at_least (option.at_least in cross body; Verilator uses at_least=1 for bins)
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// cg_at_least: 2+2+4=8 bins; 2 cross bins hit (count=1, at_least effectively 1) -> 6/8=75%
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addr = 0;
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cmd = 0;
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cg_at_least_inst.sample(); // addr0 x read
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addr = 1;
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cmd = 1;
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cg_at_least_inst.sample(); // addr1 x write
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`checkr(cg_at_least_inst.get_inst_coverage(), 75.0);
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// Sample cg_goal (option.goal in cross body; does not affect hit counting)
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// cg_goal: 2+2+4=8 bins; 2 cross bins hit -> 6/8=75%
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addr = 0;
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cmd = 0;
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cg_goal_inst.sample(); // addr0 x read
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addr = 1;
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cmd = 1;
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cg_goal_inst.sample(); // addr1 x write
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`checkr(cg_goal_inst.get_inst_coverage(), 75.0);
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// Sample cg_unsup_cross_opt
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// cg_unsup_cross_opt: 2+2+4=8 bins; 2 cross bins hit -> 6/8=75%
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addr = 0;
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cmd = 0;
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cg_unsup_cross_opt_inst.sample(); // addr0 x read
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addr = 1;
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cmd = 1;
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cg_unsup_cross_opt_inst.sample(); // addr1 x write
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`checkr(cg_unsup_cross_opt_inst.get_inst_coverage(), 75.0);
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// Sample cg_unnamed_cross
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// cg_unnamed_cross: 2+2+4=8 bins; 2 cross bins hit -> 6/8=75%
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addr = 0;
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cmd = 0;
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cg_unnamed_cross_inst.sample(); // a0 x read
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addr = 1;
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cmd = 1;
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cg_unnamed_cross_inst.sample(); // a1 x write
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`checkr(cg_unnamed_cross_inst.get_inst_coverage(), 75.0);
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// Sample cg_mixed: 10 bins total (cp_addr 2 + cp_cmd 2 + cp_solo 2 + cross ab 4)
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addr = 0; cmd = 0; mode = 0;
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cg_mixed_inst.sample(); // addr0, read, solo normal, ab(addr0_x_read)
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`checkr(cg_mixed_inst.get_inst_coverage(), 40.0); // 4/10
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addr = 0; cmd = 1; mode = 1;
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cg_mixed_inst.sample(); // addr0, write, solo debug, ab(addr0_x_write)
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addr = 1; cmd = 0; mode = 0;
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cg_mixed_inst.sample(); // addr1, read, ab(addr1_x_read)
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addr = 1; cmd = 1; mode = 1;
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cg_mixed_inst.sample(); // addr1, write, ab(addr1_x_write)
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`checkr(cg_mixed_inst.get_inst_coverage(), 100.0); // 10/10
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// Sample cg_def_cross (default bin in a crossed coverpoint, gated by iff)
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mode = 1;
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addr = 0; cmd = 0; cg_def_cross_inst.sample(); // a0, read
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addr = 2; cmd = 1; cg_def_cross_inst.sample(); // ad (default), write
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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