40 lines
891 B
Systemverilog
40 lines
891 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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logic [3:0] a;
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int b;
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int cyc = 0;
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always @(posedge clk) begin
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cyc <= cyc + 1;
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end
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covergroup cg @(posedge clk);
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coverpoint a;
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coverpoint b {bins the_bins[5] = {[0 : 20]};}
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endgroup
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cg the_cg = new;
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assign a = cyc[3:0];
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assign b = cyc;
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always @(posedge clk) begin
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if (cyc == 14) begin
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$display("coverage a = %f", the_cg.a.get_inst_coverage());
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$display("coverage b = %f", the_cg.b.get_inst_coverage());
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if (the_cg.a.get_inst_coverage() != 15 / 16.0) $stop();
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if (the_cg.b.get_inst_coverage() != 4 / 5.0) $stop();
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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