54 lines
1.3 KiB
Systemverilog
54 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Hierarchical coverage in duplicate module instances
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module child (
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input clk,
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input en,
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output reg seen
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);
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`ifdef INLINE_CHILD //verilator inline_module
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`else //verilator no_inline_module
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`endif
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// The user cover and generated line/branch coverage below share one
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// module body but must produce independent counters per instance.
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same_stmt :
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cover property (@(posedge clk) en);
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always @(posedge clk) begin
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if (en) seen <= 1'b1;
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end
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endmodule
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module t (
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input clk
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);
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reg [3:0] cyc = 0;
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wire seen_a;
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wire seen_b;
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// Over 9 clock edges, u_a.en is true for cyc 0..3, so u_a should report
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// user/if coverage of 4, else coverage of 5, and line coverage of 9.
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child u_a (
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.clk(clk),
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.en(cyc < 4),
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.seen(seen_a)
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);
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// u_b.en is true only for cyc 0, so u_b should report user/if coverage of
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// 1, else coverage of 8, and line coverage of 9. These different counts
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// prove the duplicate no-inline child instances did not collapse together.
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child u_b (
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.clk(clk),
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.en(cyc == 0),
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.seen(seen_b)
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);
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always @(posedge clk) begin
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cyc <= cyc + 1'b1;
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end
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endmodule
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