115 lines
2.8 KiB
Systemverilog
115 lines
2.8 KiB
Systemverilog
// DESCRIPTION: Verilator: FSM coverage supports wide sparse state values
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input logic clk
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);
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typedef enum logic [39:0] {
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E_S0_IDLE = 40'h0000_0000_01,
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E_S1_BUSY = 40'h8000_0000_02,
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E_S2_DONE = 40'hffff_0000_03
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} enum_state_t;
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localparam logic [47:0] L_S0_IDLE = 48'h0000_0000_0001;
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localparam logic [47:0] L_S1_BUSY = 48'h8000_0000_0002;
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localparam logic [47:0] L_S2_DONE = 48'hffff_0000_0003;
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enum_state_t enum_state /*verilator fsm_reset_arc*/;
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logic rst;
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logic start;
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integer cyc;
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logic [39:0] forced_state /*verilator fsm_state*/;
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logic [39:0] forced_case_if_state /*verilator fsm_state*/;
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logic [47:0] param_state_q;
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logic [47:0] param_state_d;
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initial begin
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rst = 1'b1;
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start = 1'b0;
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cyc = 0;
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end
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 1) rst <= 1'b0;
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if (cyc == 2) start <= 1'b1;
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if (cyc == 3) start <= 1'b0;
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if (cyc == 8) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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always_ff @(posedge clk) begin
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if (rst) begin
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enum_state <= E_S0_IDLE;
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end
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else begin
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case (enum_state)
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E_S0_IDLE: enum_state <= start ? E_S1_BUSY : E_S0_IDLE;
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E_S1_BUSY: enum_state <= E_S2_DONE;
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default: enum_state <= E_S0_IDLE;
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endcase
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end
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end
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always_ff @(posedge clk) begin
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if (rst) begin
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forced_state <= 40'h0000_0000_01;
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end
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else begin
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case (forced_state)
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40'h0000_0000_01: forced_state <= start ? 40'h8000_0000_02 : 40'h0000_0000_01;
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40'h8000_0000_02: forced_state <= 40'hffff_0000_03;
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default: forced_state <= 40'h0000_0000_01;
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endcase
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end
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end
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always_ff @(posedge clk) begin
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if (rst) begin
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forced_case_if_state <= 40'h0000_0000_01;
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end
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else begin
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case (forced_case_if_state)
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40'h0000_0000_01: begin
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if (start) begin
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forced_case_if_state <= 40'h8000_0000_02;
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end
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else begin
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forced_case_if_state <= 40'h0000_0000_01;
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end
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end
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40'h8000_0000_02: forced_case_if_state <= 40'h0000_0000_01;
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default: forced_case_if_state <= 40'h0000_0000_01;
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endcase
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end
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end
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always_comb begin
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param_state_d = param_state_q;
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if (param_state_q == L_S0_IDLE) begin
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param_state_d = start ? L_S1_BUSY : L_S0_IDLE;
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end
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else if (param_state_q == L_S1_BUSY) begin
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param_state_d = L_S2_DONE;
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end
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else if (param_state_q == L_S2_DONE) begin
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param_state_d = L_S0_IDLE;
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end
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end
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always_ff @(posedge clk) begin
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if (rst) begin
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param_state_q <= L_S0_IDLE;
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end
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else begin
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param_state_q <= param_state_d;
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end
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end
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endmodule
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