148 lines
3.7 KiB
Systemverilog
148 lines
3.7 KiB
Systemverilog
// DESCRIPTION: Verilator: FSM coverage infers non-enum state space
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input logic clk,
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input logic rst,
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input logic start
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);
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localparam logic [1:0] IDLE = 2'h0;
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localparam logic [1:0] BUSY = 2'h1;
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localparam logic [1:0] DONE = 2'h2;
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localparam logic [1:0] BODY_ID = 2'h0;
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localparam logic [1:0] BODY$ID = 2'h1;
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logic [1:0] literal_state;
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logic [1:0] param_state;
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logic unbased_state;
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logic [1:0] body_symbol_state;
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logic [1:0] multiline_expr_state;
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logic [1:0] duplicate_expr_state;
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logic [1:0] duplicate_same_label_state;
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logic [1:0] duplicate_expr_first_state;
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always_ff @(posedge clk) begin
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if (rst) begin
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literal_state <= 2'h0;
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end
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else begin
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case (literal_state)
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2'h0: literal_state <= start ? 2'h1 : 2'h0;
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2'h1: literal_state <= 2'h2;
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2'h2: literal_state <= 2'h2;
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default: literal_state <= 2'h0;
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endcase
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end
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end
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always_ff @(posedge clk) begin
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if (rst) begin
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param_state <= IDLE;
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end
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else begin
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case (param_state)
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IDLE: param_state <= start ? BUSY : IDLE;
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BUSY: param_state <= DONE;
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DONE: param_state <= DONE;
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default: param_state <= IDLE;
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endcase
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end
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end
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always_ff @(posedge clk) begin
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if (rst) begin
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unbased_state <= '0;
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end
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else begin
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case (unbased_state)
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'0: unbased_state <= '1;
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'1: unbased_state <= '0;
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default: unbased_state <= '0;
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endcase
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end
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end
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always_ff @(posedge clk) begin
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if (rst) begin
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body_symbol_state <= BODY_ID;
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end
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else begin
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case (body_symbol_state)
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BODY_ID
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: body_symbol_state <= BODY$ID;
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BODY$ID: body_symbol_state <= BODY_ID;
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default: body_symbol_state <= BODY_ID;
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endcase
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end
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end
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always_ff @(posedge clk) begin
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if (rst) begin
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multiline_expr_state <= 2'h0;
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end
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else begin
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case (multiline_expr_state)
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(2'h0
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+ 2'h0): multiline_expr_state <= 2'h1;
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2'h1: multiline_expr_state <= 2'h0;
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default: multiline_expr_state <= 2'h0;
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endcase
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end
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end
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always_ff @(posedge clk) begin
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if (rst) begin
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duplicate_expr_state <= IDLE;
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end
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else begin
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/* verilator lint_off CASEOVERLAP */
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case (duplicate_expr_state)
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IDLE: duplicate_expr_state <= BUSY;
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(2'h0
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+ 2'h0): duplicate_expr_state <= BUSY;
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BUSY: duplicate_expr_state <= IDLE;
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default: duplicate_expr_state <= IDLE;
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endcase
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/* verilator lint_on CASEOVERLAP */
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end
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end
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always_ff @(posedge clk) begin
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if (rst) begin
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duplicate_same_label_state <= IDLE;
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end
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else begin
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/* verilator lint_off CASEOVERLAP */
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case (duplicate_same_label_state)
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IDLE: duplicate_same_label_state <= BUSY;
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IDLE: duplicate_same_label_state <= BUSY;
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BUSY: duplicate_same_label_state <= IDLE;
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default: duplicate_same_label_state <= IDLE;
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endcase
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/* verilator lint_on CASEOVERLAP */
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end
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end
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always_ff @(posedge clk) begin
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if (rst) begin
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duplicate_expr_first_state <= 2'h0;
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end
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else begin
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/* verilator lint_off CASEOVERLAP */
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case (duplicate_expr_first_state)
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(2'h0
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+ 2'h0): duplicate_expr_first_state <= BUSY;
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IDLE: duplicate_expr_first_state <= BUSY;
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BUSY: duplicate_expr_first_state <= 2'h0;
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default: duplicate_expr_first_state <= 2'h0;
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endcase
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/* verilator lint_on CASEOVERLAP */
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end
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end
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endmodule
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