32 lines
1.3 KiB
Python
Executable File
32 lines
1.3 KiB
Python
Executable File
#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2026 Wilson Snyder
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('vlt')
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# Reuse the same design. '--x-assign 0' makes the auto-inserted out-of-range guard on a
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# non-power-of-two bit-select a plain '(idx <= W-1) && vec[idx]' (AstLogAnd), rather than
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# the ternary '(idx <= W-1) ? vec[idx] : <x>' (AstCond) produced under the driver's default
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# '--x-assign unique'. This exercises the matcher's other guard-peel branch.
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test.top_filename = "t/t_bit_scan_loops.v"
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test.compile(verilator_flags2=['--stats', '--unroll-count', '0', '--x-assign', '0'])
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# Same lowering counts as the default run -- only the guard shape differs, not the result.
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test.file_grep(test.stats,
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r'Optimizations, Loop unrolling, Lowered priority-encoder to mostsetbitp1\s+(\d+)',
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8)
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test.file_grep(test.stats,
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r'Optimizations, Loop unrolling, Lowered count-set-bits to countones\s+(\d+)', 1)
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test.execute()
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test.passes()
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