51 lines
1.3 KiB
Systemverilog
51 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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module t;
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initial begin
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bit[229:0] qw[int]; // Wide values
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bit[229:0] qwe[int]; // Wide values - empty
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bit[229:0] qwv[$]; // Wide values - Value returns
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int qi[$]; // Index returns
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bit[229:0] w;
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qw = '{10: 1, 11: 2, 12: 2, 13: 4, 14: 3};
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qwv = qwe.min(x) with (x + 1);
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qwv = qwe.max(x) with (x + 1);
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w = qw.sum with (item + 1);
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w = qw.product with (item + 1);
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w = qwe.sum with (item + 1);
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w = qwe.product with (item + 1);
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qw = '{10: 230'b1100, 11: 230'b1010};
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w = qw.and with (item + 1);
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w = qw.or with (item + 1);
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w = qw.xor with (item + 1);
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w = qw.and() with (item + 1);
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w = qw.or() with (item + 1);
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w = qw.xor() with (item + 1);
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qwv = qw.find with (item == 2);
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qwv = qw.find_first with (item == 2);
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qwv = qw.find_last with (item == 2);
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qi = qw.find_index with (item == 2);
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qi = qw.find_first_index with (item == 2);
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qi = qw.find_last_index with (item == 2);
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// Map method (IEEE 1800-2023 7.12.5)
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qw = '{1: 100, 2: 200, 3: 300};
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qwv = qw.map(el) with (el / 100);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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