verilator/docs/gen/ex_WIDTHEXPAND_1_faulty.rst

.. comment: generated by t_lint_widthexpand_docs_bad
.. code-block:: sv
   :linenos:
   :emphasize-lines: 3

     logic [31:0] array[5];
     bit [1:0] rd_addr;
     wire [31:0] rd_value = array[rd_addr];  //<--- Warning