82 lines
1.7 KiB
Plaintext
82 lines
1.7 KiB
Plaintext
$version Generated by VerilatedVcd $end
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$timescale 1ps $end
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$scope module top $end
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$scope module t $end
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$scope module mid_a $end
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$upscope $end
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$scope module mid_b $end
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$var wire 1 & clk $end
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$var wire 32 " cnt [31:0] $end
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$scope module sub_a $end
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$var wire 1 & clk $end
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$var wire 32 # cnt [31:0] $end
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$upscope $end
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$scope module sub_b $end
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$var wire 1 & clk $end
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$var wire 32 $ cnt [31:0] $end
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$upscope $end
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$scope module sub_c $end
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$var wire 1 & clk $end
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$var wire 32 % cnt [31:0] $end
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$upscope $end
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$upscope $end
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$scope module mid_c $end
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$upscope $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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b00000000000000000000000000000000 "
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b00000000000000000000000000000000 #
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b00000000000000000000000000000000 $
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b00000000000000000000000000000000 %
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0&
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#10
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b00000000000000000000000000000001 "
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b00000000000000000000000000000010 #
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b00000000000000000000000000000010 $
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b00000000000000000000000000000010 %
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1&
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#15
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0&
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#20
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b00000000000000000000000000000010 "
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b00000000000000000000000000000100 #
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b00000000000000000000000000000100 $
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b00000000000000000000000000000100 %
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1&
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#25
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0&
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#30
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b00000000000000000000000000000011 "
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b00000000000000000000000000000110 #
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b00000000000000000000000000000110 $
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b00000000000000000000000000000110 %
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1&
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#35
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0&
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#40
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b00000000000000000000000000000100 "
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b00000000000000000000000000001000 #
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b00000000000000000000000000001000 $
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b00000000000000000000000000001000 %
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1&
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#45
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0&
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#50
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b00000000000000000000000000000101 "
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b00000000000000000000000000001010 #
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b00000000000000000000000000001010 $
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b00000000000000000000000000001010 %
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1&
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#55
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0&
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#60
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b00000000000000000000000000000110 "
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b00000000000000000000000000001100 #
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b00000000000000000000000000001100 $
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b00000000000000000000000000001100 %
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1&
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