verilator/test_regress/t/t_trace_scope_no_inline.out

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$version Generated by VerilatedVcd $end
$timescale 1ps $end
$scope module top $end
$scope module t $end
$scope module mid_a $end
$upscope $end
$scope module mid_b $end
$var wire 1 & clk $end
$var wire 32 " cnt [31:0] $end
$scope module sub_a $end
$var wire 1 & clk $end
$var wire 32 # cnt [31:0] $end
$upscope $end
$scope module sub_b $end
$var wire 1 & clk $end
$var wire 32 $ cnt [31:0] $end
$upscope $end
$scope module sub_c $end
$var wire 1 & clk $end
$var wire 32 % cnt [31:0] $end
$upscope $end
$upscope $end
$scope module mid_c $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
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