12 lines
286 B
Systemverilog
12 lines
286 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
|
|
//
|
|
// This file ONLY is placed under the Creative Commons Public Domain.
|
|
// SPDX-FileCopyrightText: 2026 Antmicro
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
module interrupt (
|
|
input logic clk_i = 1,
|
|
input logic rst_ni = 1
|
|
);
|
|
endmodule
|