52 lines
890 B
Systemverilog
52 lines
890 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Nikolai Kumar
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// SPDX-License-Identifier: CC0-1.0
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package pkg;
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class C #(
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parameter P = 0
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);
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typedef struct packed {bit [7:0] x;} my_t;
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mailbox #(my_t) mb = new();
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task run(output bit [7:0] got);
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my_t v;
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mb.get(v);
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got = v.x;
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endtask
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endclass
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endpackage
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module top;
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import pkg::*;
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initial begin
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C #(0) c0;
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C #(1) c1;
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C #(0)::my_t s0;
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C #(1)::my_t s1;
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bit [7:0] got0;
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bit [7:0] got1;
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c0 = new();
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c1 = new();
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s0.x = 8'hA5;
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s1.x = 8'h5A;
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c0.mb.put(s0);
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c1.mb.put(s1);
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c0.run(got0);
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c1.run(got1);
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if (got0 !== 8'hA5) $stop;
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if (got0 !== 8'hA5) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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