72 lines
1.5 KiB
Systemverilog
72 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2017 Josh Redford
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// SPDX-License-Identifier: CC0-1.0
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interface my_if #(
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parameter integer DW = 8
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) (
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input clk
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);
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localparam DW_LOCAL = DW;
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logic valid;
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logic [DW-1:0] data;
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modport slave_mp(input valid, input data);
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modport master_mp(output valid, output data);
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function automatic integer width();
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return $bits(data);
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endfunction
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generate
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if (DW < 4) begin : dw_lt_4_G
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function automatic integer min_width();
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return 4;
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endfunction
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end
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else begin : dw_ge_4_G
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function automatic integer min_width();
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return 8;
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endfunction
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end
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endgenerate
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endinterface
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module t (
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input wire clk,
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my_if in_if[2],
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my_if out_if[2]
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);
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assign out_if[0].valid = in_if[0].valid;
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assign out_if[0].data = in_if[0].data;
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assign out_if[1].valid = in_if[1].valid;
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assign out_if[1].data = in_if[1].data;
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my_if my_i (.clk(clk));
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initial begin
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$display(in_if[0].DW_LOCAL);
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$display(in_if[0].width());
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$display(in_if[0].dw_ge_4_G.min_width());
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$display(out_if[0].DW_LOCAL);
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$display(out_if[0].width());
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$display(out_if[0].dw_ge_4_G.min_width());
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$display(in_if[1].DW_LOCAL);
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$display(in_if[1].width());
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$display(in_if[1].dw_ge_4_G.min_width());
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$display(out_if[1].DW_LOCAL);
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$display(out_if[1].width());
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$display(out_if[1].dw_ge_4_G.min_width());
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end
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endmodule
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