74 lines
1.6 KiB
Systemverilog
74 lines
1.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2013 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Very simple test for interface pathclearing
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module t (
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input clk
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);
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integer cyc = 1;
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ifc #(2) itopa ();
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ifc #(4) itopb ();
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sub ca (
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.isub(itopa),
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.clk
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);
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sub cb (
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.isub(itopb),
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.clk
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);
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d result=%b %b\n", $time, cyc, itopa.valueo, itopb.valueo);
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`endif
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cyc <= cyc + 1;
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itopa.valuei <= cyc[1:0];
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itopb.valuei <= cyc[3:0];
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if (cyc == 1) begin
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if (itopa.WIDTH != 2) $stop;
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if (itopb.WIDTH != 4) $stop;
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if ($bits(itopa.valueo) != 2) $stop;
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if ($bits(itopb.valueo) != 4) $stop;
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if ($bits(itopa.out_modport.valueo) != 2) $stop;
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if ($bits(itopb.out_modport.valueo) != 4) $stop;
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end
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if (cyc == 4) begin
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if (itopa.valueo != 2'b11) $stop;
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if (itopb.valueo != 4'b0011) $stop;
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end
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if (cyc == 5) begin
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if (itopa.valueo != 2'b00) $stop;
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if (itopb.valueo != 4'b0100) $stop;
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end
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if (cyc == 20) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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interface ifc #(
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parameter WIDTH = 1
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);
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// verilator lint_off MULTIDRIVEN
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logic [WIDTH-1:0] valuei;
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logic [WIDTH-1:0] valueo;
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// verilator lint_on MULTIDRIVEN
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modport out_modport(input valuei, output valueo);
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endinterface
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// Note not parameterized
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module sub (
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ifc.out_modport isub,
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input clk
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);
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always @(posedge clk) isub.valueo <= isub.valuei + 1;
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endmodule
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