33 lines
629 B
Systemverilog
33 lines
629 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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interface intf;
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int status;
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function int get_status;
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return status;
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endfunction
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endinterface
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class cls;
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virtual intf i;
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function int get_status;
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return i.get_status;
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endfunction
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endclass
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module t;
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intf intf ();
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cls c;
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initial begin
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intf.status = 'hdeadbeef;
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c = new();
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c.i = intf;
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if (c.get_status !== 'hdeadbeef) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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