35 lines
592 B
Systemverilog
35 lines
592 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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package pkg;
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bit external_sig;
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endpackage
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interface iface;
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import pkg::*;
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bit local_sig;
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task local_write;
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// verilator no_inline_task
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local_sig = 1'b1;
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endtask
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task external_write;
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// verilator no_inline_task
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external_sig = 1'b1;
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endtask
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endinterface
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module t;
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iface i ();
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initial begin
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i.local_write();
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i.external_write();
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end
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endmodule
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