68 lines
1.6 KiB
Systemverilog
68 lines
1.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Two-level interface chain. Inner interface has a typedef that
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// depends on its parameter. Mid interface aliases that typedef.
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// A module aliases the alias and uses it in a packed struct, then
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// passes $bits(struct) to a width-parameterized child. All widths
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// must use the override value, not the template default.
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interface inner_if #(
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parameter int N = 1
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) ();
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typedef logic [$clog2(N)-1:0] id_t;
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endinterface
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interface mid_if #(
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parameter int N = 1
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) ();
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inner_if #(.N(N)) inner ();
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typedef inner.id_t id_t;
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endinterface
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module sink #(
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parameter int W = 1
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) (
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input logic [W-1:0] dat_i
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);
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endmodule
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module dut #(
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parameter int N = 1
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) ();
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mid_if #(.N(N)) m ();
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typedef m.id_t id_t;
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typedef struct packed {
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id_t id;
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logic [7:0] payload;
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} pkt_t;
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pkt_t pkt_var;
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localparam int W = $bits(pkt_t);
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sink #(.W(W)) s (.dat_i(pkt_var));
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endmodule
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module t;
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// N=8 gives id_t = 3 bits, so pkt_t = 3 + 8 = 11 bits.
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dut #(.N(8)) u ();
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initial begin
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if (u.W !== 11) begin
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$display("%%Error: u.W=%0d expected 11", u.W);
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$stop;
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end
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if ($bits(u.pkt_var) !== 11) begin
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$display("%%Error: $bits(u.pkt_var)=%0d expected 11", $bits(u.pkt_var));
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$stop;
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end
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if ($bits(u.s.dat_i) !== 11) begin
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$display("%%Error: $bits(u.s.dat_i)=%0d expected 11", $bits(u.s.dat_i));
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$stop;
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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