87 lines
2.5 KiB
Systemverilog
87 lines
2.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Multi-dim iface arrays with ascending (left<right) ranges and negative
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// indices. The descending/zero-based case is covered by t_iface_array_multidim*;
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// this test exercises the ascending() branch in V3Inst and negative lo() in
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// name mangling.
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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interface simple_if;
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logic [7:0] data;
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endinterface
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module t;
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// Both dims ascending, zero-based.
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simple_if asc[0:1][0:2] ();
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// Outer descending, inner ascending (mixed endianness).
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simple_if mix[1:0][0:2] ();
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// Negative indices: outer descending (1..-1), inner ascending (-2..0).
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simple_if neg[1:-1][-2:0] ();
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initial begin
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asc[0][0].data = 8'd10;
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asc[0][1].data = 8'd11;
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asc[0][2].data = 8'd12;
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asc[1][0].data = 8'd13;
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asc[1][1].data = 8'd14;
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asc[1][2].data = 8'd15;
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mix[0][0].data = 8'd20;
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mix[0][1].data = 8'd21;
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mix[0][2].data = 8'd22;
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mix[1][0].data = 8'd23;
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mix[1][1].data = 8'd24;
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mix[1][2].data = 8'd25;
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neg[-1][-2].data = 8'd50;
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neg[-1][-1].data = 8'd51;
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neg[-1][0].data = 8'd52;
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neg[0][-2].data = 8'd53;
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neg[0][-1].data = 8'd54;
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neg[0][0].data = 8'd55;
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neg[1][-2].data = 8'd56;
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neg[1][-1].data = 8'd57;
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neg[1][0].data = 8'd58;
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end
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initial begin
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#1;
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`checkd(asc[0][0].data, 8'd10);
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`checkd(asc[0][1].data, 8'd11);
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`checkd(asc[0][2].data, 8'd12);
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`checkd(asc[1][0].data, 8'd13);
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`checkd(asc[1][1].data, 8'd14);
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`checkd(asc[1][2].data, 8'd15);
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`checkd(mix[0][0].data, 8'd20);
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`checkd(mix[0][1].data, 8'd21);
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`checkd(mix[0][2].data, 8'd22);
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`checkd(mix[1][0].data, 8'd23);
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`checkd(mix[1][1].data, 8'd24);
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`checkd(mix[1][2].data, 8'd25);
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`checkd(neg[-1][-2].data, 8'd50);
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`checkd(neg[-1][-1].data, 8'd51);
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`checkd(neg[-1][0].data, 8'd52);
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`checkd(neg[0][-2].data, 8'd53);
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`checkd(neg[0][-1].data, 8'd54);
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`checkd(neg[0][0].data, 8'd55);
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`checkd(neg[1][-2].data, 8'd56);
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`checkd(neg[1][-1].data, 8'd57);
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`checkd(neg[1][0].data, 8'd58);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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