69 lines
1.8 KiB
Systemverilog
69 lines
1.8 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Multi-dim iface array where outer iface contains an inner iface.
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// outer_if oarr[A][B](), outer_if holds a single inner_if instance.
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// Access via oarr[i][j].inner.data.
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interface inner_if;
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logic [7:0] data;
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endinterface
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interface outer_if;
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inner_if inner ();
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logic [7:0] tag;
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endinterface
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module t;
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localparam int A = 2;
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localparam int B = 2;
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outer_if oarr[A-1:0][B-1:0] ();
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genvar gi, gj;
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generate
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for (gi = 0; gi < A; gi++) begin : g_a
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for (gj = 0; gj < B; gj++) begin : g_b
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initial begin
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oarr[gi][gj].tag = 8'(gi * 16 + gj);
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oarr[gi][gj].inner.data = 8'(gi * B + gj + 100);
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end
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end
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end
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endgenerate
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logic [7:0] chk_tag[A-1:0][B-1:0];
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logic [7:0] chk_inner[A-1:0][B-1:0];
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generate
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for (gi = 0; gi < A; gi++) begin : g_a_chk
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for (gj = 0; gj < B; gj++) begin : g_b_chk
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always_comb chk_tag[gi][gj] = oarr[gi][gj].tag;
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always_comb chk_inner[gi][gj] = oarr[gi][gj].inner.data;
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end
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end
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endgenerate
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initial begin
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#1;
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for (int i = 0; i < A; i++) begin
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for (int j = 0; j < B; j++) begin
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if (chk_tag[i][j] !== 8'(i * 16 + j)) begin
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$write("%%Error: oarr[%0d][%0d].tag=%0d expected %0d\n",
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i, j, chk_tag[i][j], i * 16 + j);
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$stop;
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end
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if (chk_inner[i][j] !== 8'(i * B + j + 100)) begin
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$write("%%Error: oarr[%0d][%0d].inner.data=%0d expected %0d\n",
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i, j, chk_inner[i][j], i * B + j + 100);
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$stop;
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end
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end
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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