31 lines
559 B
Systemverilog
31 lines
559 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2024 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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bit clk;
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// Gen Clock
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always #10 clk = ~clk;
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initial begin
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fork
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begin
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forever @(posedge clk);
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end
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begin
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repeat (10) @(posedge clk);
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end
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begin
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for (int i = 0; i < 6; ++i) @(posedge clk);
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end
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join_any
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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