20 lines
498 B
Systemverilog
20 lines
498 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Minimal reproducer for Verilator 5.048 internal error:
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// V3Force.cpp:216: `force` assignment has no VarRef on LHS
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//
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Zubin Jain
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// SPDX-License-Identifier: CC0-1.0
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module t;
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logic forced_sig;
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typedef struct {logic [1:0] d[0:1];} payload_t;
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payload_t s;
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initial begin
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force forced_sig = 1'b1;
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$finish(0);
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end
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endmodule
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