47 lines
843 B
Systemverilog
47 lines
843 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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module child (
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input wire drive,
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output wire observed
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);
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/*verilator no_inline_module*/
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logic value;
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assign observed = value;
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initial begin
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value = 1'b0;
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if (drive) assign value = 1'b1;
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end
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endmodule
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module t;
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wire a_observed;
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wire b_observed;
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bit done;
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child a (
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.drive(1'b1),
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.observed(a_observed)
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);
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child b (
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.drive(1'b0),
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.observed(b_observed)
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);
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always @(a_observed or b_observed) begin
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if (!done && a_observed === 1'b1) begin
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done = 1'b1;
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if (b_observed !== 1'b0) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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