28 lines
524 B
Systemverilog
28 lines
524 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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module child (
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input wire i
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);
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/*verilator no_inline_module*/
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endmodule
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module t;
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child a (.i(1'b0));
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child b (.i(1'b0));
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initial begin
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force a.i = 1'b1;
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if (a.i !== 1'b1) $stop;
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if (b.i !== 1'b0) $stop;
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if (a.i === b.i) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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