49 lines
1.3 KiB
Systemverilog
49 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2026 by Antmicro.
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
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// verilog_format: on
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typedef struct {
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logic [31:0] val;
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logic [31:0] other;
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} St1;
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typedef struct {
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St1 inner;
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logic [31:0] tail;
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} St2;
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module m;
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St2 st2;
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St2 forced;
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St2 snapshot;
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initial begin
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st2.inner.val = 32'h11;
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st2.inner.other = 32'h12;
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st2.tail = 32'h13;
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forced.inner.val = 32'h21;
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forced.inner.other = 32'h22;
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forced.tail = 32'h23;
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force st2 = forced;
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snapshot = st2;
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`checkh(snapshot.inner.val, 32'h21);
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`checkh(snapshot.inner.val[0], 1'b1);
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force st2.inner.val = 32'h30;
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release st2.inner.val;
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snapshot = st2;
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`checkh(snapshot.inner.val, 32'h21);
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`checkh(snapshot.inner.val[0], 1'b1);
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`checkh(snapshot.inner.other, 32'h22);
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`checkh(snapshot.tail, 32'h23);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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