75 lines
2.3 KiB
Systemverilog
75 lines
2.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Test that illegal_bins are excluded from coverage (like ignore_bins).
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// Also tests coverpoints where all bins are ignore/illegal - get_coverage returns 100.0.
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2026 by Wilson Snyder.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t;
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logic [1:0] data;
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logic [3:0] data4;
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covergroup cg;
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coverpoint data {bins low = {0}; bins mid = {1}; bins high = {2}; illegal_bins forbidden = {3};}
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endgroup
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// cg2: illegal_bins on multi-step transitions and array notation
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covergroup cg2;
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cp_trans: coverpoint data4 {
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bins ok = {0};
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illegal_bins bad_2step = (1 => 2); // 2-step illegal transition
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illegal_bins bad_3step = (1 => 2 => 3); // multi-step illegal transition
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illegal_bins lib_default = default; // illegal_bins = default
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}
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cp_arr: coverpoint data4 {
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bins ok = {0};
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illegal_bins bad_arr[] = {8, 9, 10}; // illegal array bins
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wildcard illegal_bins wlib = {4'b1?00}; // wildcard illegal bins
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}
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endgroup
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// cg3: all bins are ignore_bins or illegal_bins - get_coverage returns 100.0
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covergroup cg3;
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cp: coverpoint data {ignore_bins ign = {0, 1}; illegal_bins ill = {2, 3};}
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endgroup
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initial begin
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automatic cg cg_inst = new;
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automatic cg2 cg2_inst = new;
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automatic cg3 cg3_inst = new;
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// Sample legal values only
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data = 0;
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cg_inst.sample();
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data = 1;
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cg_inst.sample();
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data = 2;
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cg_inst.sample();
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`checkr(cg_inst.get_inst_coverage(), 100.0);
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// Sample cg2 - only safe values, never triggering illegal bins
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data4 = 0;
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cg2_inst.sample();
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`checkr(cg2_inst.get_inst_coverage(), 100.0);
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// Sample cg3 - values that only hit ignore_bins, never illegal_bins
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data = 0;
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cg3_inst.sample();
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`checkr(cg3_inst.get_inst_coverage(), 100.0);
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data = 1;
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cg3_inst.sample();
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`checkr(cg3_inst.get_inst_coverage(), 100.0);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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