30 lines
1.0 KiB
Systemverilog
30 lines
1.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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covergroup cg;
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cp_a: coverpoint 1'b0 {bins b0 = {0}; bins b1 = {1};}
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cp_b: coverpoint 1'b0 {bins b0 = {0}; bins b1 = {1};}
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cross_ab: cross cp_a, cp_b{
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option.per_instance = 1; // unsupported for cross; triggers COVERIGN
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}
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cross_implicit: cross cp_a, var_x;
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// Non-standard hierarchical/dotted cross item: can only be a data reference
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// (implicit coverpoint), never a coverpoint. Accepted with a NONSTD warning;
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// implicit coverpoints are unsupported so the cross is dropped (COVERIGN).
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cross_hier: cross cp_a, s_cfg.m_p;
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endgroup
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typedef struct packed {logic m_p; logic h_mode;} cfg_t;
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cfg_t s_cfg = '0;
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logic var_x = 1'b0;
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cg cg_i = new;
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initial begin
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cg_i.sample();
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$finish;
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end
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endmodule
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