130 lines
3.9 KiB
Systemverilog
130 lines
3.9 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-FileCopyrightText: 2024 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Test implicit auto-bin creation (no explicit bins) and option.auto_bin_max
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// verilog_format: off
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`define stop $stop
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`define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t;
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logic [2:0] data3;
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logic [3:0] data4;
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logic [63:0] data64; // 64-bit signal
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// Test 1: auto_bin_max default (64) - creates 8 bins for 3-bit signal
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covergroup cg1;
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cp_data3: coverpoint data3;
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endgroup
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// Test 2: auto_bin_max = 4 at covergroup level - creates 4 bins: [0:1],[2:3],[4:5],[6:7]
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covergroup cg2;
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option.auto_bin_max = 4;
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cp_data3: coverpoint data3;
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endgroup
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// Test 3: auto_bin_max and at_least set at coverpoint level
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covergroup cg3;
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cp_data3: coverpoint data3 {
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option.auto_bin_max = 2; // coverpoint-level: creates 2 bins [0:3],[4:7]
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option.at_least = 3; // coverpoint-level at_least
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}
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endgroup
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// Test 4: auto-bins where all values in a range are excluded by ignore_bins
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// auto_bin_max=4 on 4-bit signal -> 4 range bins: [0:3],[4:7],[8:11],[12:15].
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// ignore_bins {[0:3]} excludes all values in the first range -> that bin is skipped.
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covergroup cg4;
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option.auto_bin_max = 4;
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cp: coverpoint data4 {
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ignore_bins ign = {[0 : 3]}; // first range excluded from coverage
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}
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endgroup
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// Test 5: auto-bins on a 64-bit coverpoint with auto_bin_max=4
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covergroup cg5;
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option.auto_bin_max = 4;
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cp_data64: coverpoint data64;
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endgroup
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// Test option.auto_bin_max at covergroup level: creates 4 bins [0:1],[2:3],[4:5],[6:7]
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covergroup cg6;
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option.auto_bin_max = 4;
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cp_data3: coverpoint data3;
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endgroup
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initial begin
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cg1 cg1_inst;
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cg2 cg2_inst;
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cg3 cg3_inst;
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cg4 cg4_inst;
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cg5 cg5_inst;
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cg6 cg6_inst;
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cg1_inst = new;
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cg2_inst = new;
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cg3_inst = new;
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cg4_inst = new;
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cg5_inst = new;
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cg6_inst = new;
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data3 = 0;
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cg1_inst.sample();
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`checkr(cg1_inst.get_inst_coverage(), 12.5); // 1/8 bins hit
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data3 = 3;
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cg1_inst.sample();
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`checkr(cg1_inst.get_inst_coverage(), 25.0); // 2/8 bins hit
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data3 = 0;
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cg2_inst.sample();
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`checkr(cg2_inst.get_inst_coverage(), 25.0); // 1/4 bins hit: [0:1]
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data3 = 4;
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cg2_inst.sample();
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`checkr(cg2_inst.get_inst_coverage(), 50.0); // 2/4 bins hit: [0:1],[4:5]
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// cg3: at_least=3 at coverpoint level; both samples have count=1 < 3 -> 0% throughout
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data3 = 1;
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cg3_inst.sample();
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`checkr(cg3_inst.get_inst_coverage(), 0.0);
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data3 = 5;
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cg3_inst.sample();
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`checkr(cg3_inst.get_inst_coverage(), 0.0);
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// Sample valid (non-ignored) values for cg4
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// cg4: auto_bin_max=4 creates 4 bins [0:3],[4:7],[8:11],[12:15].
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// ignore_bins ign={[0:3]} excludes [0:3] values; Verilator keeps all 4 bins in denominator.
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// 3 of 4 bins hit -> 75% (the [0:3] bin is included in denominator but can never be hit)
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data4 = 4;
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cg4_inst.sample(); // [4:7] bin
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data4 = 8;
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cg4_inst.sample(); // [8:11] bin
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data4 = 12;
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cg4_inst.sample(); // [12:15] bin
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`checkr(cg4_inst.get_inst_coverage(), 75.0);
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// Sample cg5: 64-bit coverpoint - SKIP: Verilator 64-bit bin boundary bug causes 100% at first sample
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data64 = 64'h0;
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cg5_inst.sample();
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data64 = 64'h1111111111111111;
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cg5_inst.sample();
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data64 = 64'hffffffffffffffff;
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cg5_inst.sample();
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data3 = 0;
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cg6_inst.sample();
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`checkr(cg6_inst.get_inst_coverage(), 25.0); // 1/4 bins hit: [0:1]
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data3 = 7;
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cg6_inst.sample();
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`checkr(cg6_inst.get_inst_coverage(), 50.0); // 2/4 bins hit: [0:1],[6:7]
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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