66 lines
1.2 KiB
Systemverilog
66 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: User coverage per-instance records for the same statement
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module child (
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input clk,
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input en
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);
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reg observed = 1'b0;
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reg [3:0] count = 0;
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same_stmt:
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cover property (@(posedge clk) en);
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always @(posedge clk) begin
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observed <= en;
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if (en) begin
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count <= count + 1'b1;
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end else begin
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count <= count;
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end
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end
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endmodule
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module wrap (
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input clk,
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input en
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);
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child dut_b (
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.clk(clk),
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.en(en)
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);
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endmodule
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module tb;
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reg clk = 0;
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reg [3:0] cyc = 0;
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// Same user cover statement at two different hierarchy points.
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// Expected with per_instance: dut_a count=4, wrap_b.dut_b count=1.
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child dut_a (
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.clk(clk),
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.en(cyc < 4)
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);
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wrap wrap_b (
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.clk(clk),
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.en(cyc == 0)
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);
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always @(posedge clk) begin
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cyc <= cyc + 1'b1;
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end
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always #1 clk = !clk;
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always @(posedge clk) begin
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if (cyc == 8) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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