68 lines
1.5 KiB
Systemverilog
68 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: FSM coverage ignores unrelated datapath comparisons
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module datapath_only #(
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parameter logic [15:0] MASK = 16'hff00,
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parameter logic [15:0] MATCH = 16'h1200
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) (
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input logic [6:0] a,
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input logic b,
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input logic [15:0] data,
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output logic concat_hit,
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output logic masked_hit
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);
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assign concat_hit = ({a, b} == 8'h00);
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assign masked_hit = (data & MASK) == MATCH;
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endmodule
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module t #(
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parameter logic [15:0] MASK = 16'hff00,
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parameter logic [15:0] MATCH = 16'h1200
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) (
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input logic clk,
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input logic rst,
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input logic go,
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input logic [6:0] a,
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input logic b,
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input logic [15:0] data,
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output logic busy,
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output logic hit,
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output logic concat_hit,
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output logic masked_hit
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);
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typedef enum logic [1:0] {
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IDLE,
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RUN,
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DONE
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} state_t;
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state_t state;
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always_ff @(posedge clk) begin
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if (rst) begin
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state <= IDLE;
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end
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else begin
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case (state)
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IDLE: if (go) state <= RUN;
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RUN: state <= DONE;
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DONE: state <= IDLE;
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default: state <= IDLE;
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endcase
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end
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end
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assign busy = (state != IDLE);
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assign hit = (data & MASK) == MATCH;
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datapath_only datapath_only_u (
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.a(a),
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.b(b),
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.data(data),
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.concat_hit(concat_hit),
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.masked_hit(masked_hit)
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);
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endmodule
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