156 lines
3.4 KiB
Systemverilog
156 lines
3.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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// verilator lint_off WIDTHEXPAND
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class Impl;
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rand bit [63:0] x, y;
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rand bit [31:0] g;
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constraint c {
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g inside {[1 : 10]};
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y == 64'h100;
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y != 0 -> x inside {[y - g : y]};
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}
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endclass
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class Neg; // inside under logical-not
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rand bit [63:0] x, y;
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rand bit [31:0] g;
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constraint c {
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g inside {[1 : 10]};
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y == 64'h100;
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y != 0 -> !(x inside {[y - g : y - 1]});
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}
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endclass
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class LAnd; // inside as a logical-and operand
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rand bit [63:0] x, y;
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rand bit [31:0] g;
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constraint c {
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g inside {[1 : 10]};
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y == 64'h100;
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(x inside {[y - g : y]}) && (x[0] == 1'b0);
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}
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endclass
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class Nest; // nested implication a -> (b -> inside)
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rand bit [63:0] x, y;
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rand bit [31:0] g;
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rand bit a, b;
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constraint c {
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g inside {[1 : 10]};
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y == 64'h100;
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a == 1;
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b == 1;
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a -> (b -> x inside {[y - g : y]});
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}
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endclass
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class CondCtx; // inside as a ?: condition
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rand bit [63:0] x, y;
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rand bit [31:0] g;
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rand bit s;
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constraint c {
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g inside {[1 : 10]};
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y == 64'h100;
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(x inside {[y - g : y]}) ? (s == 1'b1) : (s == 1'b0);
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}
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endclass
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class Ctl; // all-32-bit control
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rand bit [31:0] x, y, g;
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constraint c {
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g inside {[1 : 10]};
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y == 32'h100;
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y != 0 -> x inside {[y - g : y]};
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}
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endclass
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class DistRange; // mixed-width dist range bound
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rand bit [63:0] x, y;
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rand bit [31:0] g;
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constraint c {
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g inside {[1 : 10]};
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y == 64'h100;
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x dist {
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[y - g : y] := 1,
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5 := 1
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};
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}
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endclass
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class Bare; // bare narrow variable as a bound
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rand bit [63:0] x, y;
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rand bit [31:0] g;
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constraint c {
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g inside {[1 : 10]};
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y == 64'h100;
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y != 0 -> x inside {[g : y]};
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}
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endclass
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module t;
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Impl im;
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Neg ng;
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LAnd la;
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Nest ne;
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CondCtx cx;
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Ctl ct;
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DistRange dr;
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Bare br;
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int ok;
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initial begin
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im = new;
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ng = new;
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la = new;
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ne = new;
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cx = new;
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ct = new;
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dr = new;
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br = new;
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for (int i = 0; i < 20; ++i) begin
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ok = im.randomize();
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`checkd(ok, 1);
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if (im.x < (64'h100 - im.g) || im.x > 64'h100) `checkd(0, 1);
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ok = ng.randomize();
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`checkd(ok, 1);
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if (ng.x >= (64'h100 - ng.g) && ng.x <= 64'hFF) `checkd(0, 1);
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ok = la.randomize();
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`checkd(ok, 1);
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if (la.x < (64'h100 - la.g) || la.x > 64'h100 || la.x[0] !== 1'b0) `checkd(0, 1);
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ok = ne.randomize();
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`checkd(ok, 1);
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if (ne.x < (64'h100 - ne.g) || ne.x > 64'h100) `checkd(0, 1);
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ok = cx.randomize();
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`checkd(ok, 1);
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if (cx.s !== ((cx.x >= (64'h100 - cx.g)) && (cx.x <= 64'h100))) `checkd(0, 1);
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ok = ct.randomize();
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`checkd(ok, 1);
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if (ct.x < (32'h100 - ct.g) || ct.x > 32'h100) `checkd(0, 1);
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ok = dr.randomize();
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`checkd(ok, 1);
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if (dr.x != 5 && (dr.x < (64'h100 - dr.g) || dr.x > 64'h100)) `checkd(0, 1);
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ok = br.randomize();
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`checkd(ok, 1);
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if (br.x < {32'h0, br.g} || br.x > 64'h100) `checkd(0, 1);
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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// verilator lint_on WIDTHEXPAND
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