38 lines
736 B
Systemverilog
38 lines
736 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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class Foo;
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rand int abcd;
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endclass
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class Bar;
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rand Foo foo_arr[];
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function new();
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foo_arr = new[12];
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foreach (foo_arr[i]) foo_arr[i] = new;
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endfunction
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constraint c {
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foo_arr.size() == 10;
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foreach (foo_arr[i]) foo_arr[i].abcd < 8;
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}
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endclass
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module t;
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Bar bar;
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initial begin
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bar = new();
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bar.randomize();
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if (bar.foo_arr.size() != 10) $stop;
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foreach (bar.foo_arr[i]) begin
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if (bar.foo_arr[i] >= 8) $stop;
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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