30 lines
616 B
Systemverilog
30 lines
616 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Nikolai Kumar
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// SPDX-License-Identifier: CC0-1.0
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module t;
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logic clk = 0;
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logic [1:0] data[1:0];
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logic [1:0] snap[1:0];
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clocking cb @(posedge clk);
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input data;
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endclocking
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always @(cb) snap <= cb.data;
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always #5 clk = ~clk;
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initial begin
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data[0] = 2'd1;
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data[1] = 2'd2;
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@(posedge clk);
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@(posedge clk);
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if (snap[0] !== 2'd1 || snap[1] !== 2'd2) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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