30 lines
777 B
Systemverilog
30 lines
777 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2026 Nikolai Kumar
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// SPDX-License-Identifier: CC0-1.0
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class monitor;
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bit clk, enable, fired;
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task run();
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forever @(posedge clk iff enable) fired = 1;
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endtask
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endclass
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module t;
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monitor mon = new;
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always #5 mon.clk = ~mon.clk;
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initial begin
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fork mon.run(); join_none
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repeat(4) @(posedge mon.clk);
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if (mon.fired !== 0) begin $display("FAIL: fired before iff guard satisfied"); $stop; end
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mon.enable = 1;
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repeat (2) @(posedge mon.clk);
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if (mon.fired !== 1) begin $display("FAIL: did not fire when guard true"); $stop; end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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