24 lines
491 B
Systemverilog
24 lines
491 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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virtual class Base;
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pure virtual function void f0();
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endclass
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virtual class Child extends Base;
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pure virtual function void f1();
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endclass
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class Impl extends Child;
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virtual function void f0();
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endfunction
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virtual function void f1();
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endfunction
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endclass
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module t;
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endmodule
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