50 lines
995 B
Systemverilog
50 lines
995 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t;
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reg a;
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reg b;
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reg c;
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reg d;
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reg control;
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reg clock = 0;
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always @(posedge clock) {a, b, c, d} = 4'h3;
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always @(control)
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if (control) begin
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assign {a, b, c, d} = 4'h2;
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end
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else begin
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deassign {a, b, c, d};
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end
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always begin
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#2;
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clock = ~clock;
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end
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initial begin
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#3;
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`checkh({a, b, c, d}, 4'h3)
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#2;
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control = 1;
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#1;
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`checkh({a, b, c, d}, 4'h2)
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#3;
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control = 0;
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#2;
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`checkh({a, b, c, d}, 4'h3)
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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