43 lines
892 B
Systemverilog
43 lines
892 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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bit a, b;
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logic g = 0;
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default clocking @(posedge clk);
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endclocking
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// verilog_format: off
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sequence s_nonedge;
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@(g) a ##1 b;
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endsequence
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sequence s_ref;
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@(posedge clk) a;
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endsequence
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// Legal but its endpoint topology is not buildable, so the wait could never
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// resume; rejected rather than silently ignored.
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sequence s_or;
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@(posedge clk) (a ##1 b) or (a ##2 b);
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endsequence
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// verilog_format: on
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// Legal: p is never asserted, so s_ref stays referenced outside any
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// assertion property, which is not yet supported.
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property p;
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s_ref;
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endproperty
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initial begin
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@s_nonedge;
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@s_or;
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end
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endmodule
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