64 lines
1.5 KiB
Systemverilog
64 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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module t;
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bit clk;
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bit a;
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bit b;
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int n;
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// Goto non-constant max bound.
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property p_goto_nonconst;
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@(posedge clk) a |-> b [-> 1: n];
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endproperty
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// Nonconsecutive non-constant max bound.
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property p_nc_nonconst;
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@(posedge clk) a |-> b [= 1: n];
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endproperty
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// Goto non-constant min bound.
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property p_goto_min_nonconst;
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@(posedge clk) a |-> b [-> n: 2];
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endproperty
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// Nonconsecutive non-constant min bound.
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property p_nc_min_nonconst;
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@(posedge clk) a |-> b [= n: 2];
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endproperty
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// Goto max < min.
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property p_goto_bad_order;
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@(posedge clk) a |-> b [-> 3: 1];
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endproperty
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// Nonconsecutive max < min.
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property p_nc_bad_order;
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@(posedge clk) a |-> b [= 3: 1];
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endproperty
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// Goto min < 0 is a hard error.
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property p_goto_neg_min;
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@(posedge clk) a |-> b [-> -1: 2];
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endproperty
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// Nonconsecutive min < 0 is a hard error.
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property p_nc_neg_min;
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@(posedge clk) a |-> b [= -1: 2];
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endproperty
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a1 :
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assert property (p_goto_nonconst);
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a2 :
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assert property (p_nc_nonconst);
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a3 :
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assert property (p_goto_min_nonconst);
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a4 :
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assert property (p_nc_min_nonconst);
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a5 :
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assert property (p_goto_bad_order);
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a6 :
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assert property (p_nc_bad_order);
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a7 :
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assert property (p_goto_neg_min);
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a8 :
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assert property (p_nc_neg_min);
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endmodule
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